1. Technical Field of the Invention
This disclosure generally relates to a bitline structure of a semiconductor device, and more specifically, to a damascene bitline structure of a semiconductor device and a method for fabricating the same that reduces parasitic capacitance and that improves process margins by forming a stud type capping layer.
2. Description of the Related Art
As the size of semiconductor devices is reduced, the line width of bitlines and data lines is also decreased, thereby increasing the bitline resistance. To solve this problem, a metal film like tungsten is often used for bitline materials, instead of a metal silicide such as tungsten silicide (WSix).
FIG. 1 is a diagram illustrating a semiconductor device of the prior art that has a COB (Capacitor Over Bitline) structure. FIGS. 2A–2D and FIGS. 3A–3D are cross-sectional diagrams illustrating fabrication methods for a conventional semiconductor device, wherein FIGS. 2A–2D are cross-sectional views taken along a line IA–IA′ of FIG. 1, and FIGS. 3A–3D are cross-sectional views taken along a line IB–IB′ of FIG. 1. FIG. 4 is a cross-sectional diagram of the conventional semiconductor device, taken along a line IC–IC′ of FIG. 1.
Referring to FIG. 2A and FIG. 3A, a semiconductor substrate 100 including active regions 101 and field regions is provided. Through a conventional STI (Shallow Trench Isolation) process, STI isolation films 105 are formed in the field regions of the semiconductor substrate 100.
Referring to FIG. 3A, gates 110 are formed on the semiconductor substrate 100, each including a gate insulating film 111, a gate electrode material 113, and a capping layer 115 in stack and a spacer 117 formed on a sidewall.
Referring to FIGS. 2A and 3A, after forming a first inter-insulation layer 120 on the entire surface of the substrate including the gates 110, contacts 125 exposing portions of the active regions 101, for instance, SACs (Self-Aligned Contacts) are formed. And, contact pads 130 comprised of a poly-silicon film and others are formed on the contacts 125. At this time, though not shown in the drawings, the contact pads 130 are electrically connected to impurity regions of a predetermined conductivity type formed in the active regions 101.
Then, after depositing a second inter-insulation layer 140 on the first inter-insulation layer 120, bitline contact holes 145 are formed to expose corresponding ones of the contact pads 130, that is, the corresponding contact pads that are to be connected with bitlines in a subsequent process.
After depositing a metal film for a contact pad, for example, a tungsten film on the entire surface of the substrate including the bitline contact holes 145, the tungsten film is etched by a chemical-mechanical polishing process (CMP) or an etch back process, thereby forming bitline contact pads 150 in the bitline contact holes 145.
Referring to FIG. 2B and FIG. 3B, a conductive material 161 for a bitline, such as a tungsten film, and the bitline capping layer 165, such as a silicon nitride film, are sequentially deposited on the second inter-insulation layer 140 and patterned to form bitlines 160. Each bitline includes the stacked conductive material 161 and the capping layer 165. The bitline 160 is electrically connected to the bitline contact pad 150 formed in the bitline contact holes 145. An insulating film, such as a silicon nitride film, for a bitline spacer is deposited on the second inter-insulation layer 140 including the bitlines 160 and etched to form bitline spacers 170.
Referring to FIG. 2C and FIG. 3C, a third inter-insulation layer 180 is formed on a second inter-insulation layer 140 including the bitlines 160. By etching the second and the third inter-insulation layers 140 and 180, storage node contact holes 185 are formed to expose corresponding contact pads of the contact pads 130, that is, the corresponding contact pads connected to the storage node contact pads to be formed in a subsequent process.
After depositing a poly-silicon film on the third inter-insulation layer 180 to fill the storage node contacts 185, storage node contact pads 190 are formed through a CMP method and others. The storage node contact pad 190 is electrically connected to the contact pad 130 through the storage node contact holes 185. Then, storage nodes 200 of capacitors connected to the storage node contact pads 190 are formed.
The prior art method forms bitlines by etching a metal film like a tungsten film through a photoetching process, thus there may be restrictions on an etching of a metal pattern having a small line/spacer due to high integration as well as increased process complexity.
In addition, since cleaning solutions that include OH radicals such as SC1 (Standard Cleaning 1), with excellent detergency for particles and polymers, can not be used while patterning a metal film for forming bitlines, it is impossible to perfectly remove particles during the cleaning process, thereby causing defects.
To solve the above problems of the prior art, a method of forming bitlines through a damascene process has been suggested. When forming bitlines of a semiconductor device having a COB structure with a damascene process, it is necessary to surround the bitlines by forming materials having etching selectivity with an inter-insulation layer of an oxide film, for instance, a capping layer and a spacer comprised of a silicon nitride film on tops and side walls of the bitlines, in order to protect the bitlines during the next process of forming a storage node contact hole.
A technology of protecting the bitlines by perfectly surrounding a damascene bitline with the capping layer and the spacer has been suggested in Korean Patent Laid Open Report No. 2001-55685. The above technology forms a bitline that is perfectly surrounded by a spacer comprised of a silicon nitride film, thereby obtaining process margins by protecting the bitlines during the storage node contact hole process. However, it causes the increase of parasitic capacitance since a silicon nitride film between neighboring bitlines has a higher dielectric constant than an oxide film.
Embodiments of the invention address these and other disadvantages of the prior art.